Electric Bug Zapper

None of us likes bugs at home. To kill these flying insects, they should first be attracted and then electrocuted. Bug zapper is one such device with a high-voltage electrocuting circuit and an insect-attracting UV lamp of 365 nm wave-length. This ultraviolet fluorescent lamp is mounted in the middle of the cabinet and a pair of carefully spaced, electrically insulated, charged wire grids surround the light. When an insect comes close enough to the mesh pair, an electrical arc is formed, the dielectric breaks down and current flows through the insect’s body. Electrocuting the insect doesn’t require it to touch both the wires as an arc forms in the air gap over 1800V.
In the schematic, the grid is charged to 1800V by the voltage multiplier built around diodes D1 through D6 and capacitors C1 through C6. When a bug passes through the grid, the high grid voltage causes a discharge though the bug, the grid voltage reduces and the stored voltage kills the bug instantly.

To ignite the UV lamp, a voltage tapping is provided from the volt-age multiplier circuit. At switch-on, around 700V ionises the gas in the tubelight and capacitor C7 discharges through the tube, lowering the resistance enough to sustain continual AC current flow. C7 then continues to act as the ballast.

Assemble the circuit on a general-purpose PCB and enclose in a small rectangular cabinet. Fix the UV lamp and the assembled PCB inside the cabinet. Mount the high-voltage grid outside the cabinet on the front panel. Now your electric bug zapper is ready to use.

EFY warning. As the circuit works on a high voltage, don’t touch the grid with bare hands to avoid electric shock, which can be dangerous!

Robot That Breathes Life Into AC Ducts

“To regard old problems from a new angle requires creative imagination and marks real advance in science.”

—Albert Einstein

          For commercial set-ups such as shopping malls and office complexes, which mostly have centrally air-conditioned environments, getting air-conditioners’ ducts cleaned has hitherto remained a challenge. The reasons are multiple. The equipment required to clean the ducts of these air-conditioners (ACs) are extremely expensive and bulky.

Manually doing this job is tedious and risky for the health of the person getting into these ducts. Considering that the ducts have a narrow passage, invariably, children are put into these dust-filled tunnels for cleaning—a practice that’s illegal.

Apart from these issues, the choking of AC ducts over time affects the quality of the air circulated by the AC. It also leads to more power consumption and in some cases even breakdown of the air-conditioning system.

To address these problems, Robo-soft Systems has developed DuctBot—a toy car-sized robot that measures 23 cm in length, 19 cm in width and 9 cm in height. Priced at Rs 100,000, the device is claimed to cost five times less than the versions available globally.

Some vital statistics

DuctBot is a skid-steer drive gadget weighing 2 kg. It includes high-intensity LED light and charge-coupled device (CCD) colour camera to inspect the duct and provide a live feed. The vehicle moves on wheels and has attachments for cleaning the duct. It is fitted with a motor that can be controlled and switched on and off by supplying differential voltage. The device can be controlled wirelessly using Sony PS2 joystick.

A small slot in the duct is enough to put compact DuctBot inside and inspect air ducting condition of the flooring. DuctBot can go into spaces as tight as 9.6×17.8 cm² (4×7 square inches) in cross section. Once it is inside the air duct from one end, it blows compressed air in the duct helping the filter attached at the other end to collect the dust.

The vehicle moves on wheels and has attachments for cleaning the duct. It is fitted with a motor that can be controlled and switched on and off by supplying differential voltage.

A four-member team worked on building the device, which took four years of R&D. “The device can go where no man can go and no man wants to go. What makes DuctBot one-of-its-kind product in India is that the other alternatives available are bulky, very difficult to carry and control, and require the user to be trained prior to operating these. Our system is light and easy to carry in flight. Besides, no training is required to show how a PS2 joystick works,” says Fahad Azad, managing partner, Robosoft Systems.

The technology that drives the DuctBot

“DuctBot is completely made from off-the-shelf systems available across the world. We have tried to make varied technologies work in sync with each other. It is a combination of mechanical, electronics and software engineering. The robot is designed in CAD software using embedded systems and microcontrollers and is programmed in embedded C. Our main consideration while designing the robot in CAD was whether it will be possible for us to write the code for the performance desired from the product, and will the electronics system be reliable in varied conditions?” says Azad.

“We have tried to make the device as cost-effective as possible so that the users can recover the cost of the machine in much lesser time. They can discard their old machine and go for a new one, instead of buying heavily engineered machines, which are high in maintenance and use components that become obsolete or expensive to get after some years,” he adds.

The scenario and market for duct cleaners in India

How healthy is the AC environment you are exposed to? Azad has a tip to share: “If you go to any centrally air-conditioned environment and happen to see automated air fresheners on the walls spraying the freshener regularly, it is an indication that the air quality is bad and the content of dust is so high that there is bacteria growth in the duct, causing odour in the air. “If there is no dust in the duct, there will never be bacteria and pollen formation. Just changing air filters regularly is not the solution to this problem; the ducts need to be thoroughly cleaned and disinfected.”

Are people aware of the importance of having a duct cleaner? To this, Azad says, “The issue in India is that there is no regulation or policy of the government that makes it mandatory to check and maintain indoor air quality—mostly because air-conditioning is relatively new in India. Other countries have strict regulations and quality controls, which are essential to comply with for any establishment. Companies in India do it on their own as it reduces electricity consumption and bad odour from environments.”

To market the product, RoboSoft uses the Internet as the key medium. “Our main market is the Middle East, followed by the US, Europe and Southeast-Asian countries. Our key customers include Blue Star in India and EPSCO in the Middle East,” shares Azad.

What’s in the offing?

The company has not filed for any patents so far as the team feels that the international process is very expensive and the Indian patent system is not so strong. “We intend to file for a patent soon. Right now we are bootstraped. We believe that it is the customers who bring in the money in India and not the patents. If it were software, we could have licensed it to users,” says Azad.

Azad also shares some of the other plans related to the future versions of the device: “We are planning to launch a new version of the device named DuctBot HD. It will come with an HD 1080i camera, which offers a full high-definition recording capability compared to the CCD colour camera used in the existing product.

“We have also designed a very small robot fitted with a night vision camera and microphone for National Security Guards commandos. This robot can be dropped inside any room or building before going in to preview the place. We are looking for agencies who can help us sell our products to the government.”

Digitally Adjustable Dancing Lights

You might have come across several types of adjustable dancing lights (flickering LEDs). Most of them use presets (variable resistors) to adjust the rate of switching. Being a mechanical component, the preset easily wears out with use and also introduces noise in the circuit. The circuit presented here selects different values of resistors to control the frequency of an astable multivibrator using timer IC 555.

The circuit is built around decade counter IC 4017, quad bilateral switch IC 4066 (to select the desired resistance) and timer 555. The decade counter output selects one of the resistors at the output of IC 4066. The selected resistor changes the time period of the 555 timer circuit, whose ‘on’ and ‘off’ timings are given by:
t_on = 0.693(R9+Rx)C3
t_off = 0.693RxC3

Fig. 1: Circuit for digitally adjustable dancing lights

In the present design, R9 = 1 kilo-ohm, C3 = 47 µF and Rx varies according to the output of IC1 (CD4017), which changes by pressing the switch S2 one by one.

When
Rx=R5=5.6 kilo-ohms, t_on=0.214969 second, t_off=0.182398 second
Rx=R6=10 kilo-ohms, t_on=0.358281 second, t_off=0.325710 second
Rx=R7=22 kilo-ohms, t_on=0.749133 second, t_off =0.716562 second
Rx=R8=33 kilo-ohms, t_on=1.107414 second, t_off=1.074843 second

Fig. 2: Optional circuit

Whenever you momentarily press switch S2, the output of the decade counter advances to select a higher value of resistor Rx in IC 4066, which changes the switching time of the astable multivibrator. LED1 and LED2 indicate switching ‘off’ and ‘on,’ respectively, of the multivibrator.

Assemble the circuit on a general-purpose PCB and enclose in a suitable case. Fix LEDs and switches on the front panel. Connect the optional circuit shown in Fig. 2 if higher intensity of light is needed.

FPGA Design Flow

Field-programmable gate array (FPGA) is a device that has numerous gate (switch) arrays and can be programmed on-board through dedicated Joint Test Action Group (JTAG) or on-board devices or using remote system through Peripheral Component Interconnect Express (PCIe), Ethernet, etc. FPGAs are based on static random-access memory (SRAM). The contents of the memory of an FPGA erase once the power is turned off. Usually, FPGAs can be programmed several thousands of times without the device getting faulty.

Fig. 1 shows the architecture of an FPGA. It includes logic blocks, input/output (I/O) cells, phase-locked loops/delay-locked loops (PLLs/DLLs), block RAM and interconnecting matrix. Nowadays, FPGAs are also coming up with several hard intellectual property (IP) blocks of PCIe, Ethernet, Rocket I/O, PHYs for DDR3 interfaces and processor cores (for example, PowerPC in Xilinx Virtex-5 FPGA and ARM cores in both Xilinx and Altera series FPGAs).

To level up with the new technology, both Xilinx and Altera have come up with new series of FPGAs (Virtex 7 from Xilinx and Stratix-V from Altera), which are manufactured with TSMC’s 28nm silicon technology. These FPGAs focus on a high speed with low power consumption using various parameters and bringing down the FPGA core voltage to as low as 0.9V. Along with the new FPGAs, Xilinx and Altera are also focused on improving their synthesis tools to meet the routing constraints and to analyse the timing and power consumption of the FPGA. 

Fig. 1: FPGA architecture (generic)

As the aim here is to learn the basic technique of FPGA design to work with both the tools and devices, let’s get back to the design flowthrough the steps.

Step 1: Requirement analysis and SRS preparation
Before starting work on the design, all requirements should be documented as system requirement specificatio (SRS) by designers and approved by various levels in the organisation, and most importantly, the client. During this phase, FPGA designers, along with the hardware team, should identify suitable FPGAs for the project. This is very important because designers need to know parameters such as the I/O voltage levels, operating frequency and external peripheral interfaces.

It is also important to determine which IP cores are available with the tools or FPGA family used for the project. Some IP cores are free, while others are licensed and paid for. This cost should be reviewed several times by the team before releasing it to the client and listed separately for approval from the client or management.

The SRS should contain the following (the list pertains to the FPGA only):
1. Aim of the project
2. Functionalities to be handled by the design, followed by a short description
3. A concept-level block diagram depicting the major internal peripherals/IPs of the FPGA
4. FPGA vendor, family, speed grade, package, core voltage, supported I/O levels, commercial/industrial type
5. List of blocks that will be used as IPs. Mention clearly what’s available for free with the vendor-provided IPs, hard IPs available within the FPGA and paid licensed IPs to be used
6. Type of processor interfaces used (soft processor or external processor interfaces)
7. Type of memory interfaces used
8. A section about the timing diagram of the major peripheral interfaces such as the processor interface and flash interfac
9. Type of FPGA configurationsto be used
10. Reset and clock interface planned
11. A brief summary of the estimated resources required for implementation of the logic and I/O pins to be used
12. HDL (VHDL, Verilog, ‘C’ or mixed) used for RTL coding, tools and version to be used for synthesis, implementation and simulation

Spartan-6 USB-FPGA module 1.11b

To calculate the approximate resources required, go through the IP datasheets for the resources used for each IP, and also calculate the resources used by custom RTL. There is no rule of thumb for calculating resources at this level. These can be calculated approximately based on experience, reviews or analysis. The most important thing is to get the resource requirement reviewed by the hardware team, software team and a third party several times before submitting it to the client.

Step 2: Detailed design document preparation
Once the SRS is approved by the client, the next phase is to make the detailed design document.

This document should consist of:
1. Brief introduction to the project
2. FPGA part details with proper specification
3. Detailed block diagram depicting the internal modules of the FPGA design
4. Top-level module block diagram showing input and output ports with their active levels and voltage levels which are connected to the external peripherals, connectors and debug points
5. Hierarchical tree of the modules
6. Each module should have:
   (i) Detailed explanation of the functionality
   (ii) Register information
   (iii) List of input and output ports with source and destination module name, and active level of the signal
  (iv) A block diagram/digital circuit diagram of finite-statemachines indicating how the RTL will be implemented
   (v) Clock frequency to be used, if a synchronous module is used
   (vi) Reset logic implementation
   (vii) File name which will be implemented
   (viii) Approximate FPGA resource utilisation
   (ix) Testbench for testing each module independently
7. Input system clock frequency and reset level
8. Explanation of how the internal clock frequencies are derived—using phase-locked loop (PLL) or delay-locked loop (DLL) with the input clock. Also, explain how the global clock buffers are used. Mention clock signals with their frequency and voltage levels that are driven out of the FPGA for external peripherals 
9. A simulation environment setup for the design (called ‘device under test’) with a top-level testbench. A block diagram indicating how the clock source, reset and pattern generators, and bus functional modes are connected to the top-level module under testing will be helpful here. Mention how log filesare used to register the activity of the required signal 
10. Make a page with the heading ‘FPGA Synthesis and Resource Utilisation.’ Keep it blank with a note that once the final implementation is done, this page will be updated
11. Under the heading ‘Timing Analysis,’ mention the major timing parameters of the control signals to be maintained, with a timing budget and waveform drawn manually or using timing analyser tool. Mention the major timing constraints that will be used in the UCF or QSF filesof the design 

As mentioned in Step 1, the FPGA team members, hardware and software team members and architects should review the document at several stages before releasing it to the client.

Step 3: Design entry and functional simulation
Each module owner should develop a testbench for his module, capture simulated waveforms or assertion-based log report, and get it reviewed by the team lead. Before going for synthesis, every module should be verifiedthoroughly for functionality using simulation. Regular code review will help to reduce errors and simulation time. Once the simulation of individual modules is done, the next step is to integrate the module and do full-system-level functional simulation with assertion-based log report.

Fig. 2: FPGA design flowchart

Step 4: Synthesis
If the functional simulation satisfie the requirement, the next phase is synthesis.

In this phase, the integrated project is synthesised using a vendor-specificsynthesis tool based on the optimisation settings. Whenever RTL is modifed, it is always good to complete Step 3 with unit-level and full-system functional simulation. Always follow vendor-specificcoding guidelines and library modules for better optimisation of the design. 

During this phase, synthesis tools verify the design for syntax errors and do block-level floor planning.

Step 5: Adding design constraints
Once synthesis is complete, constraints can be added to the design. These constraints are usually included in a separate fle where the designer lists out the signal with its corresponding FPGA pin number, I/O voltage levels, current-driving strength for output signals, input clock frequency, hard block or module location, timing paths to be ignored, false paths, other IP-specificconstraints recommended by the vendor, etc. This information is passed on to the placement phase.

Step 6: Placement and routing phase
Before routing, the synthesis tool maps the buffers, memory and clock buffers to the specificvendor libraries. That is, in this phase, logical blocks are translated into physical fileformat. Then, in the place-and-route process, the tool places and routes the design considering the user constraints and optimisation techniques. Timing simulation can be done at this stage to verify the functionality, so that the design meets all the functional and timing requirements.

Step 7: Programming file generation
After obtaining a satisfactory timing and functional behaviour of the design, it is time to generate the bit filethat is downloaded to the FPGA to test the functionality on the board with actual peripherals.

For each stage, the tool will provide the corresponding report files,using which the designer can analyse time delays, power, resource usage, unrouted signals and I/O pins list.

In short
To summarise the above points, the FPGA design flowis shown as a simple flow-chartin Fig. 2. There may be minor variations in the design fow during the requirement stage and the design and document preparation phase, from one organisation or project to another, but the overall FPGA design flow remains the same.

Musical Water Shower

Won’t it be nice to have music playing in the background all the while when you take a shower? This simple circuit does the same. It plays different tunes repeatedly for as long as your shower is turned on. The music starts as soon as water comes out of the shower. The music stops when you turn the shower ‘off’ and water stops coming out of it.

Fig. 1 shows the circuit of the musical water shower. It comprises transistors T1 and T2 which form a complementary amplifier pair, transistor T3 acting as a switch and a 12-tone melody generator IC M3482. The M3482 is a mask-ROM-programmed IC designed to play melodies according to the programmed data. Its inbuilt preamplifier provides a simple interface to the driver circuit formed by transistors T4 and T5. The IC can be replaced with other UM348xx series, WR630173 or WE4822 melody generator ICs.

Fig. 1: Circuit for musical water shower

The melody section receives power supply through the conduction of transistor T3 when the shower is turned on.

The overhead shower unit is fitted with two insulated copper cables AD and BC as shown in Fig. 2. Insulation of a part of the cable AD (marked A’D’) is removed. Cable AD is firmly fixed and routed along the body of shower without any shorting of the bare part with the shower body. The bare part should stretch such that the shower water falls on it when running. One end of copper cable BC is soldered to the body of shower at C. It is wound around the neck to secure it firmly. Thus the cable ends at A and B are available for connection as sensor input to the circuit of Fig. 1. Now when you open the shower tap, water falls on the bare copper wire A’D’ which makes electrical contact with the cable BC through the body of the shower which is also in contact with running water. The points A and B of cable on the shower unit are connected as sensor input to the circuit of Fig. 1. This makes the power available to the base of transistor T1, which now conducts. This makes transistors T2 and T3 conduct. Thus the power supply is available for the melody circuit (Fig. 1).

Fig. 2: Sensor arrangement

The melody generator IC is programmed to produce twelve different tunes repeatedly until the shower water is running and transistors T1, T2 and T3 are conducting. The volume of melody generator tunes can be control-led through preset VR1.

When the shower is turned off, both transistors T1 and T2 cut off and a high voltage develops at the base of pnp transistor T3. Thus transistor T3 stops conducting. This, in turn, cuts off the power supply to the melody generator circuit, which stops generating musical tunes. Since the circuit consumes virtually no power when the shower is turned off, the battery lasts long.

Assemble the circuit on a general- purpose PCB and enclose it in a plastic case with LED1 and switch S1 accessible from outside. Take the sensor wires and connect to the wires on shower at A and B ends.